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t
TSL1410R 1280 x 1 LINEAR SENSOR ARRAY WITH HOLD
t TAOS043 - AUGUST 2002
D D D D D D D D D D D
1280 x 1 Sensor-Element Organization 400 Dot-Per-Inch (DPI) Sensor Pitch High Linearity and Uniformity Wide Dynamic Range . . . 4000:1 (72 dB) Output Referenced to Ground Low Image Lag . . . 0.5% Typ Operation to 8 MHz Single 3-V to 5-V Supply Rail-to-Rail Output Swing (AO) No External Load Resistor Required Replacement for TSL1410
(TOP VIEW)
Description
The TSL1410R linear sensor array consists of two sections of 640 photodiodes, each with associated charge amplifier circuitry, aligned to form a contiguous 1280 x 1 pixel array. The device incorporates a pixel data-hold function that provides simultaneous-integration start and stop times for all pixels. The pixels measure 63.5 m by 55.5 m with 63.5-m center-to-center spacing and 8-m spacing between pixels. Operation is simplified by internal logic that requires only a serial-input (SI) pulse and a clock.
1 2 3 4 5 6 7 8 9 10 11 12 13
VPP SI1 HOLD1 CLK1 GND AO1 SO1 SI2 HOLD2 CLK2 SO2 AO2 VDD
The device is intended for use in a wide variety of applications including mark and code reading, OCR and contact imaging, edge detection and positioning, and optical encoding.
Functional Block Diagram (each section)
13 Pixel 1 (641) Integrator Reset Pixel 2 (642) Pixel 3 (643) Pixel 640 (1280) VDD
Analog Bus
_ + Sample/ Output
Output Buffer
6, 12 AO
5
GND
Switch Control Logic 3, 9 Hold Hold Q1 Q2 Q3 Q640 (Q1280)
Gain Trim 7, 11 SO
CLK SI
4,10 2,8
640-Bit Shift Register (2 each)
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TSL1410R 1280 x 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS043 - AUGUST 2002
Terminal Functions
TERMINAL NAME AO1 AO2 CLK1 CLK2 GND HOLD1 HOLD2 SI1 SI2 SO1 SO2 VDD VPP NO. 6 12 4 10 5 3 9 2 8 7 11 13 1 I I I I O O I/O O O I I Analog output, section 1. Analog output, section 2. Clock, section 1. CLK1 controls charge transfer, pixel output, and reset. Clock, section 2. CLK2 controls charge transfer, pixel output, and reset. Ground (substrate). All voltages are referenced to GND. Hold signal. HOLD1 shifts pixel data to parallel buffer. HOLD1 is normally connected to SI1 and HOLD2 in serial mode and to SI1 in parallel mode. Hold signal. HOLD2 shifts pixel data to parallel buffer. HOLD2 is normally connected to SI2 in parallel mode. Serial input (section 1). SI1 defines the start of the data-out sequence. Serial input (section 2). SI2 defines the start of the data-out sequence. Serial output (section 1). SO1 provides a signal to drive the SI2 input in serial mode. Serial output (section 2). SO2 provides a signal to drive the SI input of another device for cascading or as an end-of-data indication. Supply voltage for both analog and digital circuitry. Normally grounded. DESCRIPTION
Detailed Description
The sensor consists of 1280 photodiodes, called pixels, arranged in a linear array. Light energy impinging on a pixel generates photocurrent that is then integrated by the active integration circuitry associated with that pixel. During the integration period, a sampling capacitor connects to the output of the integrator through an analog switch. The amount of charge accumulated at each pixel is directly proportional to the light intensity on that pixel and the integration time. The output and reset of the integrators are controlled by a 640-bit shift register and reset logic. An output cycle is initiated by clocking in a logic 1 on SI. Another signal, called HOLD, is generated from the rising edge of SI1 when SI1 and HOLD1 are connected together. This causes all 640 sampling capacitors to be disconnected from their respective integrators and starts an integrator reset period. As the SI pulse is clocked through the shift register, the charge stored on the sampling capacitors is sequentially connected to a charge-coupled output amplifier that generates a voltage on analog output AO. The integrator reset period ends 18 clock cycles after the SI pulse is clocked in. Then the next integration period begins. On the 640th clock rising edge, the SI pulse is clocked out on the SO1 pin (section 1) and becomes the SI pulse for section 2 (when SO1 is connected to SI2). The rising edge of the 641st clock cycle terminates the SO1 pulse, and returns the analog output AO of section 1 to high-impedance state. Similarly, SO2 is clocked out on the 1280th clock pulse. Note that a 1281st clock pulse is needed to terminate the SO2 pulse and return AO of Section 2 to the high-impedance state. Sections 1 and 2 may be operated in parallel or in serial fashion.
AO is an op amp-type output that does not require an external pull-down resistor. This design allows a rail-to-rail output voltage swing. With VDD = 5 V, the output is nominally 0 V for no light input, 2 V for normal white level, and 4.8 V for saturation light level. When the device is not in the output phase, AO is in a high-impedance state.
The voltage developed at analog output (AO) is given by: Vout = Vdrk + (Re) (Ee)(tint) where: Vout Vdrk Re Ee tint is is is is is the analog output voltage for white condition the analog output voltage for dark condition the device responsivity for a given wavelength of light given in V/(J/cm2) the incident irradiance in W/cm2 integration time in seconds
A 0.1 F bypass capacitor should be connected between VDD and ground as close as possible to the device.
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TSL1410R 1280 x 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS043 - AUGUST 2002
Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 6 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VDD + 0.3V Input clamp current, IIK (VI < 0) or (VI > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20 mA to 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25 mA to 25 mA Voltage range applied to any output in the high impedance or power-off state, VO . . . -0.3 V to VDD + 0.3 V Continuous output current, IO (VO = 0 to VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25 mA to 25 mA Continuous current through VDD or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 mA to 40 mA Analog output current range, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25 mA to 25 mA Maximum light exposure at 638 nm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mJ/cm2 Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25C to 85C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Recommended Operating Conditions
MIN Supply voltage, VDD Input voltage, VI High-level input voltage, VIH Low-level input voltage, VIL Wavelength of light source, Clock frequency, fclock Sensor integration time, Serial, tint Sensor integration time, Parallel, tint Setup time, serial input, tsu(SI) Hold time, serial input, th(SI) (see Note 1) Operating free-air temperature, TA Load capacitance, CL Load resistance, RL NOTE 1: SI must go low before the rising edge of the next clock pulse. 300 3 0 VDD x 0.7 0 400 5 0.162 0.082 20 0 0 70 330 NOM 5 MAX 5.5 VDD VDD VDD x 0.3 1100 8000 100 100 UNIT V V V V nm kHz ms ms ns ns C pF
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TSL1410R 1280 x 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS043 - AUGUST 2002
Electrical Characteristics at fclock = 1 MHz, VDD = 5 V, TA = 25C, p = 640 nm, tint = 5 ms, RL = 330 , Ee = 12.5 W/cm2 (unless otherwise noted) (see Note 2)
PARAMETER Vout Vdrk PRNU Analog output voltage (white, average over 1280 pixels) Analog output voltage (dark, average over 1280 pixels) Pixel response nonuniformity Nonlinearity of analog output voltage Output noise voltage Re Vsat SE DSNU IL IDD IIH IIL Ci Ci Responsivity Analog output saturation voltage Saturation exposure Dark signal nonuniformity Image lag Supply current High-level input current Low-level input current Input capacitance, SI Input capacitance, CLK TEST CONDITIONS See Note 3 Ee = 0 See Note 4 See Note 5 See Note 6 See Note 7 VDD = 5 V, RL = 330 VDD = 3 V, RL = 330 VDD = 5 V, See Note 8 VDD = 3 V, See Note 8 All pixels, Ee = 0, See Note 9 See Note 10 VDD = 5 V, Ee = 0 VDD = 3 V, Ee = 0 VI = VDD VI = 0 25 25 78 4.5 2.5 0.4% 1 112 4.8 2.8 155 90 0.05 0.5% 30 25 45 40 10 10 mA A A pF pF 0.15 V nJ/cm 2 V mVrms V/ (J/cm 2) MIN 1.6 0 TYP 2 0.1 MAX 2.4 0.3 20% UNIT V V
NOTES: 2. All measurements made with a 0.1 F capacitor connected between VDD and ground. 3. The array is uniformly illuminated with a diffused LED source having a peak wavelength of 640 nm. 4. PRNU is the maximum difference between the voltage from any single pixel and the average output voltage from all pixels of the device under test when the array is uniformly illuminated at the white irradiance level. PRNU includes DSNU. 5. Nonlinearity is defined as the maximum deviation from a best-fit straight line over the dark-to-white irradiance levels, as a percent of analog output voltage (white). 6. RMS noise is the standard deviation of a single-pixel output under constant illumination as observed over a 5-second period. 7. Re(min) = [Vout(min) - Vdrk(max)] / (Ee x tint) 8. SE(min) = [Vsat(min) - Vdrk(min)] x Ee x tint) / [Vout(max) - Vdrk(min)] 9. DSNU is the difference between the maximum and minimum output voltage for all pixels in the absence of illumination. 10. Image lag is a residual signal left in a pixel from a previous exposure. It is defined as a percent of white-level signal remaining after a pixel is exposed to a white condition followed by a dark condition: IL + V out (IL) * V drk V out (white) * V drk 100
Timing Requirements (see Figure 1 and Figure 2)
MIN tsu(SI) th(SI) tpd(SO) tw tr, tf Setup time, serial input (see Note 11) Hold time, serial input (see Note 11 and Note 12) Propagation delay time, SO Pulse duration, clock high or low Input transition (rise and fall) time 50 0 500 20 0 50 NOM MAX UNIT ns ns ns ns ns
NOTES: 11. Input pulses have the following characteristics: tr = 6 ns, tf = 6 ns. 12. SI must go low before the rising edge of the next clock pulse.
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TSL1410R 1280 x 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS043 - AUGUST 2002
Dynamic Characteristics over recommended ranges of supply voltage and operating free-air temperature (see Figures 7 and 8)
PARAMETER ts tpd(SO) Analog output settling time to 1% Propagation delay time, SO1, SO2 TEST CONDITIONS RL = 330 , CL = 50 pF MIN TYP 120 50 MAX UNIT ns ns
TYPICAL CHARACTERISTICS
CLK
SI1 Internal Reset 18 Clock Cycles Integration Not Integrating 1281 Clock Cycles tint Integrating
AO
Hi-Z
tw CLK tsu(SI)
SI
SO
AO
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Hi-Z
Figure 1. Timing Waveforms (serial connection)
1
2
640
641 5V 2.5 V 0V
5V 50% 0V th(SI) tpd(SO) tpd(SO)
ts Pixel 1 Pixel 640
Figure 2. Operational Waveforms (Each Section)
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TSL1410R 1280 x 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS043 - AUGUST 2002
TYPICAL CHARACTERISTICS
NORMALIZED IDLE SUPPLY CURRENT vs FREE-AIR TEMPERATURE
2 IDD -- Normalized Idle Supply Current 400 500 600 700 800 900 1000 1100
PHOTODIODE SPECTRAL RESPONSIVITY
1 TA = 25C 0.8 Normalized Responsivity
1.5
0.6
1
0.4
0.2
0.5
0 300
0 0 10 20 30 40 50 60 70 - Wavelength - nm TA - Free-Air Temperature - C
Figure 3
WHITE OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE
2 VDD = 5 V tint = 0.5 ms to 15 ms Vout -- Output Voltage -- V 1.5 Vout -- Output Voltage 0.09 0.10 VDD = 5 V
Figure 4
DARK OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE
tint = 0.5 ms tint = 1 ms
1
0.08 tint = 15 ms tint = 5 ms 0.07 tint = 2.5 ms
0.5
0 0 10 20 30 40 60 50 TA - Free-Air Temperature - C 70
0.06 0 10 20 30 40 60 50 TA - Free-Air Temperature - C 70
Figure 5
Figure 6
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TSL1410R 1280 x 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS043 - AUGUST 2002
TYPICAL CHARACTERISTICS
SETTLING TIME vs. LOAD
600 VDD = 3 V Vout = 1 V 500 Settling Time to 1% -- ns Settling Time to 1% -- ns 470 pF 400 220 pF 300 500 470 pF 400 220 pF 300 600 VDD = 5 V Vout = 1 V
SETTLING TIME vs. LOAD
200 100 pF 100 10 pF 0
200 100 pF 100 10 pF
0
200 400 600 800 RL -- Load Resistance - W
1000
0
0
200 400 600 800 RL -- Load Resistance - W
1000
Figure 7
Figure 8
APPLICATION INFORMATION
1 2 3 4 5 6 7 8 9 10 11 12 13 VDD SO1 SI2 SI1/HOLD1/HOLD2 CLK1 and CLK2
1 2 3 4 5 6 7 8 9 10 11 12 13 VDD SI1/HOLD1 CLK1 and CLK2 AO1 SO1 SI2/HOLD2
SO2 AO1/AO2
SO2 AO2
SERIAL
PARALLEL
Figure 9. Operational Connections
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TSL1410R 1280 x 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS043 - AUGUST 2002
MECHANICAL DATA
TOP VIEW 0.100 (2,54) x 12 = 1.2 (30,48)) (Tolerance Noncumulative) 0.270 (0,69) 0.121 (0,53) 13 Places 0.075 (0,191) 0.100 (2,54) BSC
13
1.170 (29,72) 1.160 (29,46)
0.158 (4,01) 0.150 (3,81) To Pixel 1
1
0.242 (6,15) 0.222 (5,64)
0.510 (12,95) 0.490 (12,45)
0.090 (2,28) DIA (2 Places)
DETAIL A 3.535(89,79) 3.525 (89,54) 3.705 (94,11) 3.695 (93,85)
Centerline of Pixels is on the Centerline of Mounting Holes
0.130 (3,30) 0.120 (3,05)
Cover Glass (Index of Refraction = 1.52)
0.015 (0,38) Typical Free Area
Linear Array
0.048 (1,22) 0.038 (0,97)
Bonded Chip
Bypass Cap DETAIL A NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Pixel centers are in line with center line of mounting holes.
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Cover Glass
0.027 (0,690)
IIIIII IIIIII
Figure 10. TSL1410R Mechanical Specifications
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TSL1410R 1280 x 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS043 - AUGUST 2002
PRODUCTION DATA -- information in this document is current at publication date. Products conform to specifications in accordance with the terms of Texas Advanced Optoelectronic Solutions, Inc. standard warranty. Production processing does not necessarily include testing of all parameters.
NOTICE
Texas Advanced Optoelectronic Solutions, Inc. (TAOS) reserves the right to make changes to the products contained in this document to improve performance or for any other purpose, or to discontinue them without notice. Customers are advised to contact TAOS to obtain the latest product information before placing orders or designing TAOS products into systems. TAOS assumes no responsibility for the use of any products or circuits described in this document or customer product design, conveys no license, either expressed or implied, under any patent or other right, and makes no representation that the circuits are free of patent infringement. TAOS further makes no claim as to the suitability of its products for any particular purpose, nor does TAOS assume any liability arising out of the use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. TEXAS ADVANCED OPTOELECTRONIC SOLUTIONS, INC. PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN CRITICAL APPLICATIONS IN WHICH THE FAILURE OR MALFUNCTION OF THE TAOS PRODUCT MAY RESULT IN PERSONAL INJURY OR DEATH. USE OF TAOS PRODUCTS IN LIFE SUPPORT SYSTEMS IS EXPRESSLY UNAUTHORIZED AND ANY SUCH USE BY A CUSTOMER IS COMPLETELY AT THE CUSTOMER'S RISK.
LUMENOLOGY is a registered trademark, and TAOS, the TAOS logo, and Texas Advanced Optoelectronic Solutions are trademarks of Texas Advanced Optoelectronic Solutions Incorporated.
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TSL1410R 1280 x 1 LINEAR SENSOR ARRAY WITH HOLD
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